Title:
MULTIPLE CONVERSION METHOD AND DEVICE THEREOF
Document Type and Number:
Japanese Patent JP3420924
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a multiple conversion method with which the latch timing is not limited by an input frame signal by setting set of delay data to be used for the multiple conversion among those delay data strings which have been prepared in number which is equivalent to the number of stages corresponding to a reference conversion cycle and then latching the set of data in the prescribed latch timing, that is decided regardless of the input frame signal.
SOLUTION: A shift register stage 1 successively delays input data and outputs delay data strings which are equivalent to the number of stages corresponding to a reference conversion cycle, that is decided based on the relation between the bit width of the input data and that of the output data. An input frame phase decision means 2 decides the specific phase of the reference conversion cycle in which the input frame signal showing the head position of the input data is located. Then the means 2 sets a set of delay data from among delay data strings to be used it for the multiple conversion. An output data output means 3 latches the set of delay data in a prescribed latch timing that has been decided, irrespective of the input frame signal and then outputs this latching result.
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Inventors:
Yudo Wada
Masami Hagio
Masami Hagio
Application Number:
JP35970597A
Publication Date:
June 30, 2003
Filing Date:
December 26, 1997
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
H03M9/00; H04J3/00; H04J3/06; (IPC1-7): H03M9/00; H04J3/00; H04J3/06
Domestic Patent References:
| JP2223241A | ||||
| JP8307404A | ||||
| JP6390927A |
Attorney, Agent or Firm:
Nobuyuki Kudo