Title:
MULTIPLYING CIRCUIT
Document Type and Number:
Japanese Patent JPS6041804
Kind Code:
A
Abstract:
Multiplying circuit for multiplying a first signal x(t) by a periodic second signal y(t) and being particularly suitable for use as an amplitude demodulator in a stereo decoder or in a phase-locked loop. It comprises N signal channels 26(.), each receiving the first signal x(t) and each producing a channel signal. Each signal channel is formed by, arranged in cascade, a switched-capacitor circuit 28(,;1. 28(.;2), 29(.), the circuit included in the signal channel having numberk being controlled by a train of control pulses g(k,i) which each have a finite duration and occur with a repetition period To and at instants to+k(To/N)+iTo wherei = ...-2,-1,0,1,2,3,...,means29(.),31, 30 for multiplying the amplitude of the signal x(t) by a constant weighting factor W(k) which is equal to y(tok[To/N]), pulsereshaping means 29(.), 30, 31 for converting a pulse applied thereto into a pulse having a predetermine duration. The channel signals thus obtained are added together in an adder device 30, 31 to form a sum signal. This sum signal is sampled in a sampling arrangement34(1), 34(2), 35 at instants comprised within the interval between the end of a control pulse g(k,i) and the beginning ofthe subsequent control pulse g(k+1,i).
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Inventors:
ARUSUURU HERUMANUSU MARIA FUAN
Application Number:
JP14702984A
Publication Date:
March 05, 1985
Filing Date:
July 17, 1984
Export Citation:
Assignee:
PHILIPS NV
International Classes:
G06G7/16; H03D1/22; H03H19/00; H04H20/88; (IPC1-7): G06G7/16; H03D1/22; H03H19/00; H04H5/00
Attorney, Agent or Firm:
Akihide Sugimura
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