PURPOSE: To suppress the increase in the circuit scale attended with the increase in number of stages by using in common a computing element varying a count of a counter of each stage in the multistage counter, allowing a multiplexer section to select sequentially a count output and to be provided to the computing element and using the result of arithmetic operation for a succeeding count.

CONSTITUTION: A selection control signal 11 is active till a count A of a 1st stage counter reaches K and a multiplexer section S5 outputs an input of a terminal B1. A selection section S1 selects an output from an adder 10, a flip- flop D1 counts up one by one the count A and counts up the count A from K0 to K and then restores to the K0. The input to the terminal B1 is outputted to a terminal Q when the terminal A1 is active in selection sections S2-S4 respectively and similarly the input to the terminal B2 is outputted to the terminal Q when the terminal A2 is active. The 2nd stage, 3rd stage and final 4th stage of counters are operated similarly.