Title:
N+1 FREQUENCY DIVIDING COUNTER AND ITS METHOD
Document Type and Number:
Japanese Patent JPH08307247
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide an N+1 frequency dividing counter which has a 50% duty cycle against all count values N and can be applied when the N is zero without requiring an excessive circuit. SOLUTION: An N+1 frequency dividing counter 20 is provided with a binary counter 22, a logic 1 detecting circuit 26, control logic 24, and an output flip flop 28. The counter 22 counts each half of output clock signals from the initial value to the final value. If N+1 is an even number, one full-cycle is added to each half cycle of the output clock signal. If N+1 is an odd number, a 1/2 cycle is added to each half cycle of the output clock signal. At the final count value, the control logic 24 transits the output clock signals at the rising edge or trailing edge of signals clock signals.
Inventors:
RABI SHIENKAA
ANA SONIA REON
ANA SONIA REON
Application Number:
JP12644996A
Publication Date:
November 22, 1996
Filing Date:
April 22, 1996
Export Citation:
Assignee:
MOTOROLA INC
International Classes:
H03K23/00; H03K21/10; H03K23/58; H03K23/64; (IPC1-7): H03K23/00; H03K23/64
Attorney, Agent or Firm:
Yoshiaki Ikeuchi
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