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Patent Searching and Data


Title:
METHOD FOR CONFIGURING INTEGRATED CIRCUIT DEVICE AND LOGIC CIRCUIT
Document Type and Number:
Japanese Patent JPH08307246
Kind Code:
A
Abstract:

PURPOSE: To attain post and large scale revision of logic circuits in the integrated circuit device provided with a programmable circuit.

CONSTITUTION: A programmable circuit 11 acquires initial circuit data from a ROM 12 in advance to configure a data input circuit. An external controller 2 provides an output of a program signal and a configuration address to the programmable circuit 11 on the opportunity of an input of a configuration command. The programmable circuit 11 receives circuit data corresponding to the received configuration address from a circuit data storage section 21 through DMA transfer to conduct configuration based thereon. When the programmable circuit 11 is revised into a circuit having other function, a reset signal and a configuration address of a circuit to be revised are outputted from the external controller 2 to the programmable circuit 11 and the similar processing to above is conducted.


Inventors:
URAKAWA TADATOMO
Application Number:
JP10920895A
Publication Date:
November 22, 1996
Filing Date:
May 08, 1995
Export Citation:
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Assignee:
NIPPON ELECTRIC ENG
International Classes:
G06F11/22; G11C7/00; H01L21/82; H03K19/173; H03K19/177; (IPC1-7): H03K19/177; G06F11/22; G11C7/00; H01L21/82; H03K19/173
Attorney, Agent or Firm:
Suzuki Masayoshi