Title:
【発明の名称】積分器回路
Document Type and Number:
Japanese Patent JP3082090
Kind Code:
B2
Abstract:
A switched current integrator circuit is provided with a feedforward input (32) which is connected to the input of a first current memory cell (T31, T32, S31, C31) during a portion phi 1 of each sampling period and to the input of a second current memory cell (T33, T34, S32, C32) during a portion phi 2 of each sampling period. The signal to be integrated is fed to a second input (31) connected to the input (T33) of the second current memory cell and the output (T32) of the first current memory cell. A first output (T34) of the second current memory cell is fed back to the input (T31) of the first current memory cell. A second output (T35) if the second current memory cell is coupled to the integrator output (33).
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Inventors:
John Barry Hughes
Application Number:
JP11883790A
Publication Date:
August 28, 2000
Filing Date:
May 10, 1990
Export Citation:
Assignee:
Konin Krekka Philips Electronics NV
International Classes:
G06G7/186; G06G7/184; G11C27/02; H03H19/00; (IPC1-7): G06G7/186; H03H19/00
Domestic Patent References:
| JP1243717A | ||||
| JP61264812A | ||||
| JP59202598A | ||||
| JP5667480A |
Attorney, Agent or Firm:
Susumu Tsugaru (6 people outside)