PURPOSE: To reduce the maximum peak current flowing through a power source line at the time of retrieval operations.

CONSTITUTION: A memory matrix being used is divided in the direction of a bit string into a first divided memory matrix block consisting of word memories MW1a TO MW128a and a second divided memory matrix block consisting of word memories MW1b TO MW128b. The retrieval operation of the first divided memory matrix block is performed by a retrieval enabling signal ENa and the retrieval operation of the second divided memory matrix block is performed by a retrieval enabling signal ENb whose timing is shifted with respect to the retrieval enabling signal ENa. The peak current at the time of retrieval operations is reduced by performing retrieval operations whose timings are shifted each other at every divided memory matrix block.