Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP3013624
Kind Code:
B2
Abstract:
PURPOSE: To protect an inner circuit from electrostatic pulses, by forming contact between a metal wiring layer and a source-drain diffusion layer, via an intermediate wiring layer whose resistance is larger than that of the metal wiring.
CONSTITUTION: The drain diffusion layer 3d or the source diffusion layer 3s of an NMOS transistor Mn is connected with a contact wiring layer composed of a WSix layer 8 via first contact holes 7 formed in a first interlayer insulating film 6. The WSix film 8 is connected with an aluminum based wiring layer 12 (out) or 12 (gnd), via second contact holes 10 formed in a second interlayer insulating film 9. The first contact holes 7 and the second contact holes 10 are alternately wired on the same diffusion layers, and the same contact holes are not formed on both sides of a gate electrode. Many electrode elements are connected in parallel, so that the influence of a wiring layer of high resistivity upon an inner circuit can be restrained to be little.
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Inventors:
Masayuki Ohashi
Application Number:
JP23322592A
Publication Date:
February 28, 2000
Filing Date:
September 01, 1992
Export Citation:
Assignee:
NEC
International Classes:
H01L21/8238; H01L21/768; H01L27/02; H01L27/092; (IPC1-7): H01L21/8238; H01L21/768; H01L27/092
Domestic Patent References:
| JP61296757A | ||||
| JP6324642A | ||||
| JP5102410A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)