Title:
OUTPUT BUFFER CIRCUIT
Document Type and Number:
Japanese Patent JP3036482
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce the generation of a noise at the time of switching without reducing current driving capability in the constant state of a transistor by providing a transition gate voltage controlling means for cramping the inter-gate and source voltage of the transistor at a constant potential.
SOLUTION: An output buffer part 3A is provided with a transition gate control circuit 31 constituted of a P channel MOS transistor P4 whose source is connected with a power source VDD2 and whose gate is connected with an output terminal TO, and a Zener diode D1 whose anode is connected with the gate of a transistor P3 and whose cathode is connected with the drain of the transistor P4. A level shift, signal (d) of a level shift part 2 is maintained at a potential obtained by subtracting the potential of the Zener diode D1 from the potential of the power source VDD2 through the transistor P4 and the Zener diode D1. That is, the inter-gate and source voltage of a transistor P3 is cramped at a potential close to an inter-gate and source voltage corresponding to driving capability in a normal time.
Inventors:
Kazuki Yamada
Application Number:
JP25223797A
Publication Date:
April 24, 2000
Filing Date:
September 17, 1997
Export Citation:
Assignee:
NEC
International Classes:
H03K19/0185; H03K19/0175; (IPC1-7): H03K19/0175
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)