Title:
CMOS LOGIC CIRCUIT
Document Type and Number:
Japanese Patent JP3019805
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a CMOS logic circuit that is operated at a high speed with a small delay where a leak current is not increased.
SOLUTION: Base coupling capacitors Cc1, Cc2 are provided between back gates corresponding to gates of a PMOS transistor(TR) P1 and an NMOS TR N1 being components of a CMOS inverter. Thus, a threshold level of the PMOS TR P1 is increased and a threshold level of the NMOS TR N1 is decreased at the rise of an input signal 1 and the threshold level of the PMOS TR P1 is decreased and the threshold level of the NMOS TR N1 is increased at the half of the input signal 1, then a delay in the CMOS inverter is decreased. Furthermore, increase in a leakage current is suppressed by increasing the threshold level of the TRs whose state changes from ON to OFF.
Inventors:
Masahiro Nomura
Masakatsu Yamashina
Masakatsu Yamashina
Application Number:
JP16286797A
Publication Date:
March 13, 2000
Filing Date:
June 19, 1997
Export Citation:
Assignee:
NEC
International Classes:
H01L27/04; H01L21/822; H01L27/092; H03K19/017; H03K19/094; H03K19/0948; (IPC1-7): H03K19/0948
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)