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Title:
FORMATION OF MULTILAYER WIRING IN SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH088339
Kind Code:
A
Abstract:

PURPOSE: To obtain a method for forming a multilayer wiring in a semiconductor element without causing insufficient coverage or etching at the time of formation of an upper layer wiring by eliminating SOG crack at a recess in a lower layer wiring part thereby forming a smooth insulating film.

CONSTITUTION: The method for forming a multilayer wiring in a semiconductor element by applying SOG a plurality of times in order to flatten the lower layer wiring part comprises a step for applying SOG 44 by predetermined number minus 1 times to a recess in a first insulating film 43 deposited on a first layer wiring 42 to form a thick SOG 44 between the first layer wirings 42, a step for firing the thick SOG 44 to generate cracks therein, a step for applying the final SCG 44A to fill the cracks thus forming a thin SOG 44A, and a step for firing the thin SOG 44A.


Inventors:
UCHIDA HIROAKI
Application Number:
JP14004594A
Publication Date:
January 12, 1996
Filing Date:
June 22, 1994
Export Citation:
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Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
H01L21/768; H01L21/316; (IPC1-7): H01L21/768; H01L21/316
Attorney, Agent or Firm:
Mamoru Shimizu (1 person outside)



 
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