PURPOSE: To enable the judgment of the quality of a complementary type semiconductor integrated circuit by analyzing not only a power source leak current relationship between through a pair of power source terminals but also a relationship with signal delay time therein.

CONSTITUTION: Measurement of a power source leak current flowing through a pair of power source terminals is performed with no signal inputted into the complementary type semiconductor integrated circuit and the measurement of signal delay time in the complementary type semiconductor integrated circuit with a signal inputted in the complementary type semiconductor integrated circuit. Then, relationship between the power source leak current and the signal delay time as measured is determined with the power source leak current taken on the axis of ordinate and the signal delay time on the axis of abscissa. In the complementary type semiconductor integrated circuit determined to be acceptance, the larger the value of the power source leak current grows, the more the signal delay time lowers naturally. In the complementary type semiconductor integrated circuit determined to be rejection, the signal delay time will not lower naturally even if the value of the power source leak current becomes larger.