Title:
THREE-DIMENSIONAL CONNECTING METHOD FOR ELECTRONIC COMPONENT PACKAGE AND THREE-DIMENTIONAL COMPONENT FORMED THEREBY
Document Type and Number:
Japanese Patent JPH077130
Kind Code:
A
Abstract:
PURPOSE: To eliminate the limitation of connecting a pad provided on a semiconductor chip and to attain cost reduction by stacking up packages mounted on a grid, while incorporating components, and interconnecting these package, using their laminated surfaces. CONSTITUTION: Pckages 2 provided with pins 21, while incorporating components are respectively mounted on a heat-conducting grid 4. The packages 2 provided with a grid 4 are piled up, and the packages 2 are integrated by an insulating material 5. A laminate 3, which is generated as a result, is cut so that the pin 21 of the package 2 or one side face at least of grid 4 can be plagiarized with the side face of the laminate 3, and the electrical connection between the pins 21 is formed on the side face of the laminate 3. Thus, the density of component can be improved, and the package 2 provided with the connecting pin 21 can be used on any piece of surfaces. Moreover, this method can be applied for laminating any number of the packages 2.
More Like This:
| JPH09260391 | MANUFACTURE FOR SEMICONDUCTOR DEVICE |
| JP2005203429 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE |
Inventors:
KURISUCHIYAN BUARU
Application Number:
JP28014893A
Publication Date:
January 10, 1995
Filing Date:
October 13, 1993
Export Citation:
Assignee:
THOMSON CSF
International Classes:
H01L23/52; H01L25/00; H01L25/065; H01L25/10; H01L25/11; H01L25/18; (IPC1-7): H01L25/00; H01L23/52
Attorney, Agent or Firm:
Takashi Koshiba
Next Patent: コンデンサ