SEQUENTIALLY APPROXIMATING TYPE ANALOG/DIGITAL CONVERTER IN SINGLE COMPARATOR TYPE WHICH IS NOT SENSITIVE TO HYSTERESIS

Japanese Patent JPH066224

A

PURPOSE: To prevent an A/D conversion error caused from MOS threshold shift generated between successive approximation tests of the MSB group and the LSB group of binary weighted bit capacitors. CONSTITUTION: Two amplifiers 32 and 30 are provided to amplify a voltage change occurred on a charge distribution conductor 12 connected to bit capacitors between the successive approximation tests of each of the bit capacitors of the MSB group and the LSB group. The output of each amplifier is applied to the MOSFET of the input stage of a comparator 36. By sufficiently increasing the gain of the amplifier 30, when a MOS threfhold shift generated before is divided into its gain and it is referred back to the input of the amplifier 30, it is set to be smaller than the voltage change generated on the charge distribution conductor 12 between the successive approximation tests of the bit capacitors of the LSB group.

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JIMII AARU NAIRAA
BERUNDO EMU RANDERU

JP4548893A

January 14, 1994

March 05, 1993

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BURR BROWN CORP

H03M1/14; H03M1/06; H03M1/34; H03M1/74; H03M1/46; H03M1/80; (IPC1-7): H03M1/34; H03M1/14; H03M1/74

Kyozo Yuasa (5 people outside)

Next Patent: PARALLEL D/A CONVERTER CIRCUIT