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Title:
CLOCK SYNCHRONIZING DEVICE
Document Type and Number:
Japanese Patent JPH0653826
Kind Code:
A
Abstract:

PURPOSE: To provide a clock synchronizing device capable of supplying a sampling clock synchronized with a wide range clock applied from the external and reduced at its jitter to a D/A converter, an A/D converter, or the like.

CONSTITUTION: This clock synchronizing device is provided with a highly stable voltage control oscillator 1, a reference clock phase comparator 2, a voltage control oscillator 3, an external clock phase comparator 6, an n-ary counters 5, an up/down counter 7 for controlling the frequency dividing ratio (n) of the counter 5. The frequency dividing ratio of the counter 5 is changed based on a compared result between the frequency of an external clock and an output signal from the oscillator 3, the frequency of an output signal from the counter 5 is compared with that of an output signal from the oscillator 1 by the comparator 2 and an output signal from the comparator 2 is used as the control voltage of the oscillator 3 to provide a clock with small jitter.


Inventors:
SEKI NOBUYUKI
Application Number:
JP20480892A
Publication Date:
February 25, 1994
Filing Date:
July 31, 1992
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03L7/10; G11B20/14; H03L7/183; H03L7/197; (IPC1-7): H03L7/183; H03L7/10
Attorney, Agent or Firm:
Akira Kobiji (2 outside)



 
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