NAND FLASH MEMORY UNIT, NAND FLASH MEMORY ARRAY, AND METHODS FOR OPERATING THEM

Japanese Patent JP2013157074

A

To reduce a threshold shift of a select transistor caused by holes injected into or drawn out of a trapping layer under a gate of said transistor during erasure, in a NAND flash memory.

A NAND flash memory unit includes: a string 20 of memory cells connected in series; at least one select transistor 22 coupled to both ends of the string; and at least one erase transistor 24 coupled to the at least one select transistor and an S/D region. The select transistor is for selecting the string of memory cells, and the erase transistor is for reducing a threshold shift of the select transistor.

JP2812202	[Title of Invention] Semiconductor storage device
WO/2004/061863	PROGRAMMABLE MEMORY ARRAY STRUCTURE INCORPORATING SERIES-CONNECTED TRANSISTOR STRINGS AND METHODS FOR FABRICATION AND OPERATION OF SAME
JPH10261296	NON-VOLATILE SEMICONDUCTOR MEMORY AND DATA READ-OUT METHOD

LIN WEI
SHIRATA RIICHIRO
NINA MITIUKHINA
KUO TSAI-HAO

JP2012162932A

August 15, 2013

July 23, 2012

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PHISON ELECTRONICS CORP

G11C16/04; H01L21/336; H01L21/8247; H01L27/115; H01L29/788; H01L29/792

JP2011054267A	2011-03-17
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JP2011096341A	2011-05-12
JP2006155750A	2006-06-15
JP2009283799A	2009-12-03
JP2006512776A	2006-04-13
JP2005071558A	2005-03-17
JP2013016781A	2013-01-24
JP2012146350A	2012-08-02
JP2009026447A	2009-02-05
JP2013140953A	2013-07-18
JP2013089282A	2013-05-13
JP2011170956A	2011-09-01

WO2011114503A1

2011-09-22

Longhua International Patent Service Corporation

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