Title:
NOISE REDUCING CIRCUIT
Document Type and Number:
Japanese Patent JP3299026
Kind Code:
B2
Abstract:
PURPOSE: To provide a satisfactory noise reducing effect for a moving image signal or a voice signal upon which a high frequency noise is superimposed.
CONSTITUTION: A noise level detection circuit 14 detects a noise component at a line part, where there is no image signal, in the vertical blanking term of an input video signal, converts its level into a DC voltage and outputs it. The signal levels of E1 and E2 are decided by a voltage comparator circuit 15 and the identification signals of (+), (-) and '0' are provided. When the signal level of E1 is higher than that of E2 (E1>E2), a subtracted signal (E1-E3) is selected, in the inverse case of E1<E2, an added signal (E1+E3) is selected and when those signal levels are equal (E1=E2), the signal E1 is selected as it is by a selective addition/subtraction circuit 18.
Inventors:
Koichi Yamaguchi
Yoshinori Izumi
Seiichi Goshi
Masahide Naemura
Jun Fukuda
Yoshinori Izumi
Seiichi Goshi
Masahide Naemura
Jun Fukuda
Application Number:
JP4012594A
Publication Date:
July 08, 2002
Filing Date:
March 10, 1994
Export Citation:
Assignee:
Japan Broadcasting Corporation
International Classes:
H04N5/21; H03H17/00; H03H17/02; H04B1/10; (IPC1-7): H04N5/21; H03H17/00; H04B1/10
Domestic Patent References:
| JP3297277A | ||||
| JP430676A | ||||
| JP5276526A |
Attorney, Agent or Firm:
Yoshikazu Tani (1 person outside)