PURPOSE: To decrease ununiformity in cell current caused during simultaneous reading of 8 bits without decreasing the degree of integration and to improve the reliability of a storage device, by providing eight memory transistors as one unit such that a source region to which the eight memory transistors are connected commonly is contacted with a metallic interconnection at a position deviated from the end of the common source region.

CONSTITUTION: A byte selecting gate of a byte selecting transistor for selecting each byte is formed by extending a selecting gate 15 of the selecting transistor. A source region 19 of the byte selecting transistor is connected to a control gate 14 of a memory transistor by means of metallic interconnection. For reading data from a desired byte, 1 V for example is applied to an 8 bit drain, 5 V to the selecting gate 15 and an arm potential to the control gate 14, so as to detect whether each memory transistor is ON or OFF. Since the contact section between the source region and the metallic interconnection is located at the center of the 8 bits, increase in voltage at the source can be halved in comparison with prior arts. Accordingly, ununiformity of cell current in each byte also can be reduced to half.