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Title:
NONVOLATILE MEMORY
Document Type and Number:
Japanese Patent JPS58199491
Kind Code:
A
Abstract:

PURPOSE: To improve the reliability of a nonvolatile memory by connecting the sources and bulks of the 1st and the 2nd MNOS elements to the output terminal of a cross coupling type flip-flop and the gates to the input terminal, and further connecting resistance loads to the drains of the MNOS elements.

CONSTITUTION: MOS transistors (TR) M1WM8 constitute the cross coupling type NOR gate flip-flop which has a set terminals S and a reset terminal R. The nodes Q and Q' of this flip-flop are connected to the sources S1 and S2 and bulks B1 and B2 of the 1st and the 2nd MNOS elements N1 and N2, and the nodes Q and Q' are connected complementarily to the gates G1 and G2 of the elements N1 and N2. Further, the drains D1 and D2 of elements N1 and N2 are connected to a connection terminal Vss through the resistance loads Z1 and Z2. Consequently, secure operation and high reliability are obtained and stored information is read easily at repower-on operation.


Inventors:
NAKADA YASUO
Application Number:
JP8062382A
Publication Date:
November 19, 1983
Filing Date:
May 13, 1982
Export Citation:
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Assignee:
SONY CORP
International Classes:
H01L27/11; G11C14/00; H01L21/8244; H01L21/8247; H01L29/788; H01L29/792; (IPC1-7): G11C11/40; H01L27/10; H01L29/78
Attorney, Agent or Firm:
Sada Ito



 
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