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Title:
NONVOLATILE SEMICONDUCTOR MEMORY AND DATA PROGRAMMING METHOD THEREFOR
Document Type and Number:
Japanese Patent JP3462894
Kind Code:
B2
Abstract:

PURPOSE: To prevent an increase in size by reducing column lines by supplying a large current to a cell at the time of reading, implanting electrons in a floating gate, averaging a threshold voltage, an electron emission, and separating a latch circuit from a cell array in a nonvolatile semiconductor memory.
CONSTITUTION: The nonvolatile semiconductor memory comprises cell blocks connected in series with FGFETs to store '0' or '1' in an FG electron state, and block selecting FFTs connected in series with one-side ends of the blocks. A bit check FET is connected in series in the block to decide a logical state of the cell in a cell block bundle. A negative threshold voltage is allocated to the more cells of the bundle to store the '0' and '1'. One column line is commonly used for two adjacent memory cell bundles. A voltage to the FG is sequentially raised, implantation of electrons is stopped at a predetermined quantity of the electrons to be implanted, electrons are emitted, then the electrons are implanted, and one of pieces of binary information is stored. On the other hand, in order to prevent an increase in a chip size, a latch circuit is formed at a position separate from a cell array.


Inventors:
Hiroshi Iwahashi
Application Number:
JP23557693A
Publication Date:
November 05, 2003
Filing Date:
August 27, 1993
Export Citation:
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Assignee:
Toshiba Corporation
Toshiba Microelectronics Corporation
International Classes:
G11C17/00; G11C16/02; G11C16/04; G11C16/12; H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): G11C16/02; G11C16/04; H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
JP5182474A
JP5144277A
JP528780A
JP62241199A
JP62162299A
JP274069A
JP6224499A
JP1159895A
JP5182481A
JP61127179A
JP294198A
JP56680A
JP3147596A
Attorney, Agent or Firm:
Kazuo Sato (3 others)