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Title:
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JP2013084318
Kind Code:
A
Abstract:

To provide a nonvolatile semiconductor memory device capable of accurately executing read-out operation by preventing a leak current.

The nonvolatile semiconductor memory device includes a first conductivity type semiconductor layer and multiple second conductive type wells formed on the first semiconductor layer in such a manner as to align in a first direction. Memory blocks are arranged in each of the multiple wells. Multiple NAND cell units structured of multiple memory cells and a selection transistor connected in series are arranged in each of the multiple memory blocks. Each of multiple word lines is connected in common to the multiple NAND cell units in a memory block. Each of multiple bit lines extending in the first direction is connected to one end of a NAND cell unit existing in each of the multiple memory blocks. A source line is connected to the other end of the NAND cell unit. A well driver performs control to give a first voltage or a second voltage which is greater than the first one selectively to each of the multiple wells.


Inventors:
MAEJIMA HIROSHI
Application Number:
JP2011221500A
Publication Date:
May 09, 2013
Filing Date:
October 06, 2011
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G11C16/02; G11C16/04; G11C16/06
Attorney, Agent or Firm:
Masaru Itami
Kazuhiko Tamura
Konaga