Title:
Nonvolatile semiconductor memory
Document Type and Number:
Japanese Patent JP6042363
Kind Code:
B2
Abstract:
A nonvolatile semiconductor memory device according to one embodiment comprises: a memory cell array comprising a plurality of NAND strings, each NAND string comprising a memory string comprising a plurality of memory cells and a dummy transistor; a plurality of word lines; a dummy word line; a plurality of bit lines; a source line; and a control circuit performing an erase sequence, the erase sequence repeating an erase operation to the memory cells and the dummy transistor and an erase verify operation of confirming whether the memory cells and the dummy transistor are changed to an erased state. The control circuit is configured to be able to perform, when the erase verify operation is unpassed, a dummy transistor erase operation of selectively changing the dummy transistor to an erased state and a dummy transistor erase verify operation of confirming whether the dummy transistor is changed to an erased state.
Inventors:
Ryuta Hirai
Yasuhiro Shiino
Yasuhiro Shiino
Application Number:
JP2014043990A
Publication Date:
December 14, 2016
Filing Date:
March 06, 2014
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G11C16/04; G11C16/02
Domestic Patent References:
| JP201269205A | ||||
| JP2008146771A | ||||
| JP201165704A |
Attorney, Agent or Firm:
Kisaragi International Patent Business Corporation