To remarkably shorten a test time by providing at least one among a whole selection or a whole non-selection function of word lines on even addresses or odd addresses, and the whole selection or the whole non-selection function of bit lines on the even addresses or odd addresses.

When a basic pattern at a flash memory test time is written, first of all, a low level signal is inputted to a WLeven-E terminal and a BLeven- E terminal, and even address word lines WL0, WL2 and even address bit lines BL0, BL2 are made whole selection. Then, the write-in of the data 0 by one page is performed. Thus, the data 0 are written in memory cells on the intersected points between the word lines WL0, WL2 and the bit lines BL0, BL2, and a checker pattern is written in. Further, when a short circuit between word lines, bit lines is checked, the low level signal is inputted to the WLeven-E, and a WLodd-DisE terminals, and a word line drive circuit 1 is operated, and by monitoring a Vcc current, the short circuit is checked.