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Title:
OFFSET AUTOMATIC COMPENSATION CIRCUIT
Document Type and Number:
Japanese Patent JPS62104209
Kind Code:
A
Abstract:

PURPOSE: .To reduce automatically even an offset voltage superimposed on a signal saturated at a different saturation level by decreasing the offset voltage of a summing amplifier circuit saturated at a different saturation level into 1/(1+AK) times.

CONSTITUTION: An output voltage Vout of a summing amplifier circuit 1 is fed to an inverting amplifier circuit 2. An output voltage V3 is obtained at an output terminal V3 of the inverting amplifier circuit 2. Then an output voltage of the inverting amplifier circuit 2 is fed to the 1st-order delay element circuit 3 to obtain an output voltage V4. Denoting resistors 17, 18 of an offset detection circuit 3 as r7 and r8 respectively, then the output of the inverting amplifier circuit including a DC component being an offset voltage is integrated for a long period and amplified to r8/r7 rimes. Then the output voltage V4 of the 1st-order delay element circuit 3 is impressed to the summing amplifier circuit 1. The final offset voltage of the circuit 1 becomes an output voltage Vout reduced by 1/[1+A°(r8/r7)] times by the operation of the circuit forming a series of loops and the offset voltage is compensated automatically.


Inventors:
KIDO MITSUYASU
CHIBA TOMIO
Application Number:
JP24148485A
Publication Date:
May 14, 1987
Filing Date:
October 30, 1985
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G05B11/36; H03F3/34; H03F3/347; H03H19/00; (IPC1-7): G05B11/36; H03F3/34; H03H19/00
Attorney, Agent or Firm:
Katsuo Ogawa



 
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