Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
OFFSET COMPENSATING CIRCUIT
Document Type and Number:
Japanese Patent JPH03132885
Kind Code:
A
Abstract:

PURPOSE: To simplify the circuit constitution and to reduce the circuit scale by deriving a difference between a converted digital signal, and a digital offset value held in a register by an arithmetic circuit, and compensating an offset of an analog circuit.

CONSTITUTION: By converting an output signal for showing an offset value at the time when an analog signal inputted to an analog circuit 1 is set to zero, to a digital signal by an A/D converter 2 and holding it in a register 4, an analog output signal processed by the analog circuit 1 is converted to a digital signal by the A/D converter 2 and inputted to a digital circuit 3. In this case, by deriving a difference between the digital offset value held in the register 4 and the output digital signal of the A/D converter 2 by an arithmetic circuit 5, a digital signal whose offset is compensated can be inputted to the digital circuit 3. In such a way, the circuit scale can be reduced, and also, the automation can be executed.


Inventors:
TOKIWA KOJI
MIYOSHI SEIJI
AWATA YUTAKA
OTA SHINJI
Application Number:
JP27044989A
Publication Date:
June 06, 1991
Filing Date:
October 19, 1989
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
FUJITSU LTD
International Classes:
G06G7/12; G06J1/00; (IPC1-7): G06G7/12; G06J1/00
Attorney, Agent or Firm:
Shoji Kashiwaya (1 person outside)