PURPOSE: To produce a cache memory of large capacity, by providing a coincidence detecting terminal which is used for detecting the presence and absence of a block and combining plural one-chip cache memories.

CONSTITUTION: The cache memory of this invention is provided with a coincidence detecting terminals FS which informs other chips of existence of a block, to which a memory access request is made, and detects the presence of a block in other chips and a chip selecting terminal CS which is used for instructing that a block assignment is to be made in the said cache memory chip. Upon receiving the memory access request of a processor, the access is performed in its own chip when the requested block is found in its own chip. When the coincidence detecting terminal FS detects that the requested block cannot be found not only in its own chip but also in other chips, the requested block is loaded on the said cache memory chip if a select signal is impressed upon the chip selecting terminal CS.