OPERATING MODE SETTING CIRCUIT, LSI HAVING THE OPERATING MODE SETTING CIRCUIT, AND OPERATING MODE SETTING METHOD

Title:

OPERATING MODE SETTING CIRCUIT, LSI HAVING THE OPERATING MODE SETTING CIRCUIT, AND OPERATING MODE SETTING METHOD

Document Type and Number:

Japanese Patent JP2007171060

Kind Code:

A

Abstract:

To provide an operation mode setting circuit capable of setting a test mode/normal operation mode of LSI by using a general-use terminal, without providing an exclusive test mode setting terminal.

A logic circuit 110a performs AND operation, based on a mode signal inputted via a mode terminal TA1 and a signal acquired by delaying a system reset signal by one clock at a system reset time. The logic circuit 110a outputs a signal, showing an ordinary operation mode as long as a prescribed period Tdm in response to the system reset signal, and outputs a value of the inputted mode signal, after the lapse of the prescribed period Tdm. The mode signal is held by a selector 109a and a flip-flop 108a and is outputted to an LSI body part 200.

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Inventors:

SATO MAKOTO

Application Number:

JP2005371130A

Publication Date:

July 05, 2007

Filing Date:

December 23, 2005

Export Citation:

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Assignee:

TOSHIBA CORP

International Classes:

G01R31/3185; G01R31/28; H01L21/822; H01L27/04

Attorney, Agent or Firm:

Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto

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