Title:
OPTIMUM EQUALIZATION AND BASE LINE FLUCTUATION CORRECTION CIRCUIT
Document Type and Number:
Japanese Patent JP3631387
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To attain reduction in chip size and drive circuit by receiving a second rectified signal and a filtered signal and providing a slicer means for generating an output signal corresponding to these signals.
SOLUTION: A reception circuit 50 has an optimum filter 10 for receiving an input signal. The output of this optimum filter 10 is supplied to first and second half-wave rectifiers 52a and 52b at the some time. First and second peak detectors 56a and 56b respectively output first and second peak signal components. Then, the outputs of third and fourth peak detectors 56c and 56d are respectively applied to an offset extraction circuit 58. Finally, the outputs of third and fourth half-wave rectifiers 52c and 52d are supplied to a slicer 64, together with the filtered signal outputted from a low-pass filter 62. Then, the output of this slicer 64 becomes the output of the reception circuit 50.
Inventors:
M. Nguyen, Thailand
Application Number:
JP34471398A
Publication Date:
March 23, 2005
Filing Date:
December 03, 1998
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H03H21/00; H04B3/06; H04L25/06; (IPC1-7): H04B3/06; H04L25/06
Domestic Patent References:
| JP8223228A | ||||
| JP58198945A | ||||
| JP1064193A |
Attorney, Agent or Firm:
Kazuo Sato
Masamitsu Sato
Hidetoshi Tachibana
Yasukazu Sato
Masamitsu Sato
Hidetoshi Tachibana
Yasukazu Sato
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