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Patent Searching and Data


Title:
OUTPUT BUFFER
Document Type and Number:
Japanese Patent JPH02233018
Kind Code:
A
Abstract:

PURPOSE: To adjust separately P-channel and N-channel transistors(TRs) of the dimension of the final stage of an output buffer by adopting the constitution such that the final stage N-channel and P-channel TRs, plural pre-stages controlling the TRs separately and plural control gates inputting to the pre-stage are provided.

CONSTITUTION: CMOS TRs are adopted for the final stage TRs 11, 12 and a source of a P-channel TR connects to a power supply and a source of an N-channel TR connects to GND. The load capacitor 15 is driven by the TRs. A buffer 13 connects to each gate of the final stage TRs 11, 12. An output control logic gate 14 is controlled by output control signals 16, 17 and outputs a data signal 18.


Inventors:
KOYA HIROSHI
Application Number:
JP1989000054286
Publication Date:
September 14, 1990
Filing Date:
March 06, 1989
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03K17/16; H03K19/0185; H03K19/0948; (IPC1-7): H03K17/16; H03K19/0185; H03K19/0948