PURPOSE: To enable a sure interruption of a feed-through current by logically controlling the timing for change points of gate levels of 1st and 2nd output transistors by 1st and 2nd gate control circuits.

CONSTITUTION: By the 1st gate control circuits Q31-Q33, I5 controlling the gate level of the 1st output transistor Q21, the output is dropped under the condition that the gate level of 2nd output transistor Q22 is dropped. Therefore, at the time of reading out the high level, the gate level of 1st output transistor Q21 is changed to the low level after the gate level of 2nd output transistor Q22 is changed to the low level. By the 2nd gate control circuits Q34-Q36, I4 control ling the gate level of 2nd output transistor Q22, the output is risen under the condition that the gate level of 1st output transistor Q21 is risen. Therefore, at the time of reading out the low level, the gate level of 2nd output transistor Q22 is changed to the high level after the gate level of 1st output transistor Q21 is changed to the high level. Thus, the feed-through current is surely inter rupted.