Title:
OUTPUT CIRCUIT
Document Type and Number:
Japanese Patent JP2803448
Kind Code:
B2
Abstract:
PURPOSE: To obtain an output circuit capable of maintaining the potential state of an output terminal at a stable potential even at the time of starting up a power supply.
CONSTITUTION: The output circuit includes a level detecting circuit 8 for detecting power supply potential 10, a PMOS transistor(TR) 21 whose gate is connected to the output terminal of the circuit 8 is inserted into the potential side of a power supply terminal in an output buffer driving terminal, a capacitor 4 is inserted between the gate of the PMOS TR 21 and the potential of the terminal 10, and a capacitor 7 is inserted between a driving signal 3 and a ground terminal 9, so that an output buffer 5 is driven and the potential status of an output terminal 6 is determined. Since the PMOS TR 21 is not turned until the power supply arrives at a prescribed level at the time of its rise, the signal 3 is held at a logic 'L' level, and when the power supply arrives at the stable operation voltage of an internal circuit, the signal 3 holds the logic 'L' level since an output signal 1 is a logic 'H' level. Thereby the output terminal 6 is held at the high impedance state even at the start-up of the power supply.
Inventors:
Chiaki Kondo
Application Number:
JP8020792A
Publication Date:
September 24, 1998
Filing Date:
April 02, 1992
Export Citation:
Assignee:
NEC
International Classes:
H03K17/22; H03K17/687; H03K19/0175; (IPC1-7): H03K17/687; H03K17/22; H03K19/0175
Domestic Patent References:
| JP61248615A | ||||
| JP6187419A | ||||
| JP6444618A | ||||
| JP2130021A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)