PURPOSE: To realize high integration and low power consumption without enlarging gate width of a transistor by impressing higher potential than power source potential supplied to a power source potential node, to a gate of an output node discharge N channel type MOS transistor, when an input signal is an H level.

CONSTITUTION: An input signal 1 of an L level is impressed to a gate node NA, namely, a gate of an N channel type MOS transistor 2, through an N channel MOS transistor 4, by which the transistor 2 becomes a non-conducting state. When the signal 1 is varied from the L level to an H level, it is transferred to the gate node NA through the transistor 4, terminal potential of a capacitor 3 connected to the node NA is raised to a VCC level being lower by a threshold voltage portion than the H level, and the transistor 2 becomes a conducting state. Thereafter, when a delay time determined by a delaying circuit 8 elapses, charge stored in the capacitor 3 is raised by easy coupling, and the H level of an output node of the transistor 2 is discharged to the L level.