Title:
OUTPUT SYSTEM FOR CONTROLLER
Document Type and Number:
Japanese Patent JPH04137009
Kind Code:
A
Abstract:
PURPOSE:To prevent output from lowering even when an arithmetic cycle is extended by dividing a first cycle into plural second cycles with length shorter than that of the first cycle, and sample-outputting the same arithmetic result value at every second cycle via a hold circuit. CONSTITUTION:A digital arithmetic circuit 1 computes a controlled variable approaching a target at every cycle T2, and outputs it. However, a voltage goes down to V after the cycle T2 even when a hold value is, for example, V1 by outputting the controlled variable at every cycle T2. Therefore, an arithmetic result V1 of equivalent value is outputted at every cycle T3 that is 1/4 of the arithmetic cycle T2, and it is outputted as being held with the hold circuit 4. Since it is T2=4T3, the voltage drop of output goes to V'=1/4V, and it is enough to select the degree of setting of the cycle T3 for the cycle T2 to the level where the voltage drop V' can be neglected. In such a way, it is possible to suppress an output from going to low level even when the output cycle of arithmetic result is extended.
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Inventors:
NOMURA KAZUMASA
Application Number:
JP26013090A
Publication Date:
May 12, 1992
Filing Date:
September 27, 1990
Export Citation:
Assignee:
SHIMADZU CORP
International Classes:
G05B21/02; (IPC1-7): G05B21/02
Domestic Patent References:
| JPS5647802A | 1981-04-30 |
Attorney, Agent or Firm:
Nakamura Shigenobu