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Patent Searching and Data


Title:
OVERVOLTAGE SELF-PROTECTION TYPE SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH04125967
Kind Code:
A
Abstract:

PURPOSE: To inhibit the unreliability of the controllability of a breakover voltage by a method wherein the field strengths of the sidewall parts of an etching region are increased by a voltage lower than a breakdown strength and an avalanche breakdown is generated.

CONSTITUTION: An etching region is provided in a semiconductor layer, on which a P-N junction for bearing a breakdown strength is formed, from the main surface of the layer and the etching region is constituted of a shallow etching region of a large diameter and a deep region, which is inhered in the etching region and has a small diameter. The total amount of an impurity concentration per unit area as seen from one main surface of the semiconductor layer, in which a depletion layer is formed, is precisely controlled by a technique, such as an ion implantation or the like, for increasing the field strengths of the sidewall parts of the etching region by a voltage lower than the breakdown strength to generate an avalanche breakdown. Thereby, a current which is made to flow by the avalanche breakdown is used as a trigger current and a pilot thyristor can be made to ignite.


Inventors:
TAKADA MASANORI
SHIMIZU YOSHITERU
MURAKAMI SUSUMU
HONMA HIDEO
YOKOTA TAKESHI
Application Number:
JP24404190A
Publication Date:
April 27, 1992
Filing Date:
September 17, 1990
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L29/74; H01L29/861; (IPC1-7): H01L29/74
Attorney, Agent or Firm:
Katsuo Ogawa (2 outside)