Title:
PLLクロック信号生成回路
Document Type and Number:
Japanese Patent JP4546716
Kind Code:
B2
Abstract:
A PLL clock signal generation circuit comprising a phase comparator (101), a charge pump circuit (102), a filter circuit (103), a voltage control oscillator (104), a first divider (105) and a second divider (106), and a control circuit (107) which detects a state of the reference voltage which is output from the filter circuit (103) and controls the division ratios of the first and second dividers according to a state of the detected reference voltage. The multiple rate control circuit (107) outputs the control signal LPFOUT for changing a division ratio so that the PLL clock signal generation circuit does not deviate from a region capable of locking to a standard clock. The control circuit includes first and second Schmitt Triggers (201,202), a D flip-flop (205) and logic gates (203,204,206,207).
Inventors:
Yasuhiko Sakamoto
Nakao Yoshihiro
Nakao Yoshihiro
Application Number:
JP2003380153A
Publication Date:
September 15, 2010
Filing Date:
November 10, 2003
Export Citation:
Assignee:
Sharp Corporation
International Classes:
H03L7/10; H03L7/089; H03L7/095; H03L7/197
Domestic Patent References:
| JP2001520471A | ||||
| JP9046223A | ||||
| JP7212333A | ||||
| JP9083356A | ||||
| JP7303098A | ||||
| JP62014524A | ||||
| JP63226116A | ||||
| JP2001060870A | ||||
| JP9261042A | ||||
| JP9191247A | ||||
| JP10051304A | ||||
| JP3190428A | ||||
| JP53054456A |
Foreign References:
| US6424228 |
Attorney, Agent or Firm:
Yoshifumi Masaki