Title:
【発明の名称】書込み可能な論理アレーと同論理アレーをプログラムする方法
Document Type and Number:
Japanese Patent JP2590110
Kind Code:
B2
Abstract:
A writable logic array includes a first matrix (12,38) of gate elements. Program lines (16) connect the first array (12,38) with a second matrix (18,40) of gate elements. A plurality of switches (22), one for each program line (16), selectively couple or decouple the program lines (16) to the second matrix (18,40). Switches (22) are in turn controlled by a volatile memory (32), into which instructions may be written at the time the system into which the array is incorporated is booted up.
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Inventors:
DABURYU TEII GURIAA JUNIA
FURANKU ERU RATSUKUZUKO
FURANKU ERU RATSUKUZUKO
Application Number:
JP16958187A
Publication Date:
March 12, 1997
Filing Date:
July 07, 1987
Export Citation:
Assignee:
TEXAS INSTRUMENTS INC
International Classes:
H03K19/177; (IPC1-7): H03K19/177
Domestic Patent References:
| JP6239913A | ||||
| JP625727A | ||||
| JP6053489B2 |
Attorney, Agent or Firm:
Akira Asamura (1 person outside)