Title:
PARALLEL CALCULATION LOGICAL PROCESSOR WITH AUTOMATIC VITERVI TRACE BACK BIT STORAGE FUNCTION
Document Type and Number:
Japanese Patent JP3358996
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To perform comparative operation and trace back bit stuffing by a single cycle in a processor that executes a vitervi decoding algorithm.
SOLUTION: A processor 30 has plural accumulators 32 and plural data registers 34 connected to the former. Each of the accumulators 32 has an adder 32 and a trace back shift register 46. The adder 32 has the first and the second data inputs A, B and a data output C, and has a trace back output 78 which performs addition, subtraction and comparative operation of the data inputs A and B in accordance with plural control signals and outputs a value depending upon the result of the comparative operation. A trace back shift register 46 receives the trace back output 78. Then, if the comparative operation is performed when a vitervi mode signal 77 is one, the trace back output 78 is shifted to the trace back shift register 46.
Inventors:
Shivanand Simana Parry
PID Engineering Co., Ltd.
PID Engineering Co., Ltd.
Application Number:
JP31709798A
Publication Date:
December 24, 2002
Filing Date:
November 09, 1998
Export Citation:
Assignee:
Lucent Technologies, Inc.
International Classes:
G06F9/315; G06F9/30; H03M13/23; H03M13/41; (IPC1-7): H03M13/41; G06F9/30; G06F9/315
Domestic Patent References:
| JP5327524A | ||||
| JP1174801A | ||||
| JP8237144A |
Other References:
【文献】米国特許6330684(US,A)
【文献】米国特許5027374(US,A)
【文献】欧州特許出願公開923197(EP,A1)
【文献】欧州特許出願公開448809(EP,A1)
【文献】米国特許5027374(US,A)
【文献】欧州特許出願公開923197(EP,A1)
【文献】欧州特許出願公開448809(EP,A1)
Attorney, Agent or Firm:
Masao Okabe (11 others)
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