Title:
PARALLEL SERIAL CONVERSION CIRCUIT
Document Type and Number:
Japanese Patent JP3501732
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To solve the problems of the conventional parallel serial conversion circuits that they cause clock skew because number of flip-flop circuits and number of HCLK lines increase, when a serial number of the parallel serial conversion circuit is increased and that has had the possibility of forming a critical path, when a path delay of a latch enable pulse of parallel data is increased, and the clock speed is high because the logic of a counter decode circuit is complicated and an output fanout number increases.
SOLUTION: For example, multi-stage connection of 1/2 parallel serial conversion circuits as a conversion unit in a form of a tree configures a 1/2n parallel serial conversion circuit (n is an integer of 2 or more). This circuit can suppresses the occurrence of clock skew and prevent forming of a critical path.
Inventors:
Hidekatsu Masuko
Application Number:
JP2000190076A
Publication Date:
March 02, 2004
Filing Date:
June 23, 2000
Export Citation:
Assignee:
NEC Communication Systems, Ltd.
International Classes:
H03M9/00; H04L7/00; (IPC1-7): H03M9/00; H04L7/00
Domestic Patent References:
| JP326107A | ||||
| JP955667A | ||||
| JP6244739A |
Attorney, Agent or Firm:
Masahiko Desk (2 outside)
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