PARALLEL AND SERIAL DATA CONVERSION CIRCUIT

Japanese Patent JPH08237142

A

PROBLEM TO BE SOLVED: To convert parallel data to serial data without using a high frequency clock by using a phase locked loop to generate a clock which has the same frequency as an original system clock but a phase different from that of the original system clock. SOLUTION: A phase locked loop 17 of a conversion logic 11 receives the system clock from a system clock generator 15 to generate a synchronous clock CLK1 to be used as a phase 1. A clock buffer 20 inverts it to generate a phase 3. A delay circuit 19 delays the time period by, for example, 1/4 to generate a phase 2, and a clock buffer 21 inverts it to generate a phase 4. A register 16 latches original data D1 to D4 to obtain data d1 to d4. A parallel/ serial converter 22 samples data d1 in the phase 2 to send it in the phase 3 and samples data d2 in the phase 3 to send it in the phase 4 and samples data d3 in the phase 3 to send it in the phase 1 and samples data d4 in the phase 1 and send it in the phase 2.

FUAAHADO ROSUTAMIAN

JP31618695A

September 13, 1996

December 05, 1995

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XEROX CORP

G06F5/00; H03K5/15; H03M9/00; (IPC1-7): H03M9/00

Atsushi Nakajima (1 person outside)

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