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Patent Searching and Data


Title:
PARITY COUNTER CIRCUIT
Document Type and Number:
Japanese Patent JPS6223250
Kind Code:
A
Abstract:

PURPOSE: To count the number data of over all bits in a frame of even a high speed data by using a comparison circuit so as to compare simply the result of count of the (n-1)th frame and the n-th frame thereby obtaining the result of count for parity check.

CONSTITUTION: A counter 100 counting the number of data of a reception data and a comparator circuit 102 detecting whether or not the count of the counter just before the reception of the said frame and the count of the counter just after the number of data of the said frame is counted, are provided and an output of the comparison circuit 102 is used as the counted result of the said frame. The counted result of the said frame is changed depending on the initial state frame when the counter 100 starts the count of the said frame. Since the initial state depends on the output of the counter 100 just before the reception of the said frame, the number of data of the said frame is known by comparing the said information with the output of the counter just after the count of the said frame is finished.


Inventors:
ENDO TAKEMI
ARAI MASANORI
MIYAKI YUJI
YAMAGUCHI SHINGO
Application Number:
JP16266485A
Publication Date:
January 31, 1987
Filing Date:
July 23, 1985
Export Citation:
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Assignee:
FUJITSU LTD
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H03M13/00; H04L1/00; (IPC1-7): H03M13/00; H04L1/00
Attorney, Agent or Firm:
Sadaichi Igita