To provide a technique capable of reducing power consumption caused by a refresh operation of a semiconductor memory device.
This semiconductor memory device is provided with a refresh control part for performing a refresh operation of a memory cell array having dynamic memory cells. The refresh control part is provided with a target memory cell group setting part for setting a portion of the target memory cell group in the memory cell array, a refresh address generating part for sequentially generating a plurality of refresh addresses that can designate all memory cells in the memory cell array, and a refresh address determining part for determining whether an attention refresh address designates the target memory cell group. When it is determined that the attention refresh address designates the target memory cell group, a refresh operation is carried out on the basis of the attention refresh address.
JPS62245596 | REFRESH SYSTEM |
JPS5254342 | DYNAMIC MEMORY REFRESHING |