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Title:
パターンマッチング装置、及びコンピュータープログラム
Document Type and Number:
Japanese Patent JP5707423
Kind Code:
B2
Abstract:
The semiconductor inspection apparatus includes means for imaging a shape on a wafer or on an exposure mask; means for storing an image inspected by the imaging means; means for storing design data of the semiconductor circuit corresponding to a position on the wafer or on the exposure mask which are to be imaged by the imaging means; means for storing a design-data image obtained as a result of converting the design data into an image; means for generating a design-data ROI image by converting an interest drawing region found from a relative crude-density relation of a shape included in the design-data image into an image; and a position alignment section configured to carry out position alignment on the inspected image and the design-data image. The semiconductor inspection apparatus makes use of the design-data ROI image in order to identify a position at which the inspected image and the design-data image match each other or compute the degree of coincidence.

Inventors:
Masahiro Kitazawa
Koji Ikeda
Yuichi Abe
Junichi Taguchi
Wataru Nagatomo
Application Number:
JP2012554506A
Publication Date:
April 30, 2015
Filing Date:
December 07, 2011
Export Citation:
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Assignee:
Hitachi High-Technologies Corporation
International Classes:
G06T7/00; G06T1/00
Domestic Patent References:
JP2007121181A2007-05-17
JP2010009437A2010-01-14
JP2002267441A2002-09-18
JPH06215139A1994-08-05
JP2007121181A2007-05-17
JP2010009437A2010-01-14
JP2002267441A2002-09-18
JPH06215139A1994-08-05
Foreign References:
WO2010114117A12010-10-07
WO2010114117A12010-10-07
Attorney, Agent or Firm:
Manabu Inoue
Yuji Toda
Shigemi Iwasaki



 
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