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Patent Searching and Data


Title:
PCM INPUT INTERRUPTION BACKWARD PROTECTION CIRCUIT
Document Type and Number:
Japanese Patent JPH01300649
Kind Code:
A
Abstract:

PURPOSE: To attain digital integration circuit by providing a 2-input OR gate and a counter having a reset function and using an output of the counter so as to generate a PCM input interruption backward protection signal.

CONSTITUTION: An internal clock signal S3 and a PCM input interruption backward protection signal (backward protection signal) S2 are given to an input terminal of a 2-input OR gate 11 as the signal input, and an output terminal of the 2-input OR gate 11 is connected to a clock input terminal 13 of a counter (counter) 12 with a reset function. Moreover, the PCM input interruption alarm signal S1 is given to a reset input terminal 14 of the counter 12 as the signal input and the backward protection signal S2 is outputted at an output terminal 15 of the counter 12. Thus, since no monostable multivibrator is in use and neither a resistor nor a capacitor is needed, the digital circuit integration is facilitated.


Inventors:
EBINA KAZUO
Application Number:
JP13029388A
Publication Date:
December 05, 1989
Filing Date:
May 30, 1988
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04L25/02; H04L7/00; (IPC1-7): H04L7/00; H04L25/02
Attorney, Agent or Firm:
Masaki Yamakawa (2 outside)