Title:
PEAK DETECTOR CIRCUIT
Document Type and Number:
Japanese Patent JP3894460
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a peak detector circuit operating with a single power supply.
SOLUTION: The positive voltage VCC of a pair of power supply voltages from one power supply is applied to a terminal 34 and a ground voltage GND is applied to a terminal 35. In a peak detector circuit 21, an input signal IN is applied with a bias voltage Vbias determined by a PN junction diode 27 and an NPN junction transistor 28 and converted into a signal variable in the range from the ground voltage GND to the voltage VCC. The signal is detected by a level shift circuit 23 as a positive peak voltage with reference to the ground voltage GND and subjected to level shift before being delivered from a signal output terminal 37 to be connected with a smoothing circuit 24.
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Inventors:
Teruyoshi Koyama
Kazuaki Murota
Kazuaki Murota
Application Number:
JP20727796A
Publication Date:
March 22, 2007
Filing Date:
August 06, 1996
Export Citation:
Assignee:
Fujitsu Ten Co., Ltd.
International Classes:
G01R19/04; G11C27/00; H03D1/18; (IPC1-7): G01R19/04; G11C27/00; H03D1/18
Domestic Patent References:
| JP57124771U |
Attorney, Agent or Firm:
Keiichiro Saikyo
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