Title:
周期補正分周回路及びこれを用いた周期補正型発振回路
Document Type and Number:
Japanese Patent JP4111636
Kind Code:
B2
Abstract:
The oscillator 40 with cycle time correction includes a low accuracy oscillator 30A generating a clock CLK3, a counter 41 counting the clock CLK3 and cleared by activation of a clear signal CLR1, a register 42 storing a count CN of the counter 41 as a reference value RV in response to activation of a capture signal CAP; a comparator 43 activating a coincidence signal EQ when CN=RV, a control register 44 including a bit outputting a clear signal CLR2, a bit outputting an enable signal EN and a bit outputting a capture signal CAP, and logic circuits 45 and 46 activating the clear signal CLR1 when the clear signal CLR2 is active or when the enable signal EN and the coincidence signal EQ are both active.
Inventors:
Kinoshita Satoshi
Kunio Azuma
Kunio Azuma
Application Number:
JP23375899A
Publication Date:
July 02, 2008
Filing Date:
August 20, 1999
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03K3/353; H03K3/021; H03K23/66; H03K3/0231; H03K4/02
Domestic Patent References:
| JP10059588A |
Attorney, Agent or Firm:
Shinkichi Matsumoto