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Title:
PHASE COMPARATOR CIRCUIT AND PHASE LOCKED LOOP OSCILLATION CIRCUIT WITH THE SAME
Document Type and Number:
Japanese Patent JPH066212
Kind Code:
A
Abstract:

PURPOSE: To provide a phase comparator circuit which has the small power consumption and the high resolution by adding a 2nd pulse generating circuit and a counter to the phase comparator circuit.

CONSTITUTION: The 2nd pulse generating circuit 5 having high output frequency is provided together with a counter 6 for counting high speed pulses. The phase difference is obtained between a measured signal and a reference signal based on the output value of a latch circuit 4 and the counter 6. Furthermore the power is supplied to the circuit 5 and the counter 6 only in the operating period of the counter 6. Therefore the phase difference between the measured signal and the reference signal is obtained with high resolution by the counter 6 capable of counting the high speed pulses. Then the power consumption of a phase comparator is reduced owing to the intermittent operations of the counter 6.


Inventors:
TARUSAWA YOSHIAKI
NOJIMA TOSHIO
MUROTA KAZUAKI
Application Number:
JP2751592A
Publication Date:
January 14, 1994
Filing Date:
January 20, 1992
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H03K5/26; G01R25/08; H03D13/00; H03L7/091; H03L7/183; (IPC1-7): H03L7/091; H03K5/26
Attorney, Agent or Firm:
Masaki Yamakawa