Title:
PHASE COMPARISON TYPE BIT SYNCHRONIZATION ESTABLISHING CIRCUIT
Document Type and Number:
Japanese Patent JP3311517
Kind Code:
B2
Abstract:
PURPOSE: To recover data normally even in the presence of disturbance in the phase comparison type bit synchronization establishing circuit establishing bit phase synchronization of a transmission signal sent by the TDMA system.
CONSTITUTION: Plural phase shift means 11 shift a phase of a prescribed burst signal in a received frame respectively and a bit phase synchronization means 12 takes synchronization of bit phase, a decision means 13 decides an optimum phase shift means and a 1st selection output means 14 selects and outputs a prescribed burst signal whose phase is shifted by the optimum phase shift means. On the other hand, a storage means 15 stores an identification code of the phase shift means decided by the decision means 13 and a burst signal in succeeding reception frames or over corresponding to a prescribed burst signal is shifted by the phase shift means whose identification code is stored in the storage means 15 and a 2nd selection output means 16 selects data subject to bit phase synchronization by the bit phase synchronization means 12 and outputs the data as bit recovery data.
Inventors:
Shoichi Ohmori
Yoshinori Ishii
Yoshinori Ishii
Application Number:
JP25560994A
Publication Date:
August 05, 2002
Filing Date:
October 20, 1994
Export Citation:
Assignee:
富士通株式会社
International Classes:
H04J14/08; H04J3/06; H04L7/02; H04L7/033; H04L7/10; (IPC1-7): H04L7/02; H04J3/06; H04J14/08
Domestic Patent References:
| JP6104933A | ||||
| JP7264175A | ||||
| JP3270428A |
Attorney, Agent or Firm:
Takeshi Hattori
Previous Patent: PRODUCTION OF PLANOGRAPHIC PRINTING PLATE
Next Patent: LONG-PERIOD PREDICTION DEVICE FOR SPEECH
Next Patent: LONG-PERIOD PREDICTION DEVICE FOR SPEECH