PURPOSE: To reduce power consumption of a prescaler and a programmable frequency divider.

CONSTITUTION: A timing generating circuit 9 receives a reference signal fREF and an operation control signal S0 to provide an output of a generated control signal S1. The generated control signal S1 is given to a prescaler 31, a programmable frequency divider 41 and a phase comparator 51. On the other hand, the generated control signal S1 goes to an H level by counting the reference signal fREF for a prescribed number of times after an operation control signal S0 reaches an H level, and a raw signal fRAW is frequency-divided after the generated control signal S1 goes to H to start producing a measured signal f0, then an initial phase difference δ between the reference signal fREF and the measured signal f0 is constant independently of a timing when the operation control signal S0 goes to H. Thus, it is not required to set the timing of the operation control signal S0 going to H considerably early before a required period for time division communication.