PHASE LOCKED LOOP OSCILLATOR CIRCUIT AND PHASE COMPARATOR

Title:

PHASE LOCKED LOOP OSCILLATOR CIRCUIT AND PHASE COMPARATOR

Document Type and Number:

Japanese Patent JP2959230

Kind Code:

B2

Abstract:

PURPOSE: To provide the phase locked loop oscillator circuit in which phase comparison is implemented by using a sole phase comparator whose phase frequency demodulation sensitivity is changed in both phase locking state and phase unlocking state.
CONSTITUTION: A phase frequency difference detection circuit 31 of a phase comparator 3 receives a reference signal (b) and a comparison signal (a) from terminals R, V and outputs a detection signal whose H level duty is always the unity to a detection output terminal D and outputs a detection signal whose H level duty is decreasing as a phase difference between the two input signals a, b is increasing to a detection output terminal U. Sampling circuits 32, 33 are connected respectively to the detection output terminals U, D, from which the output signal is outputted while the H level duty is decreased when the H level duty of the input detection signal is set between 1 and 0. A differential amplifier circuit 34 receives outputs of the sampling circuits 32, 33 differentially and integrates them to obtain a phase frequency difference demodulation signal. The phase comparator 3 is used for the phase locked loop oscillation circuit and a phase shift quantity of a phase shifter 322 is controlled from a signal at a phase shift control terminal 323 in response to the synchronization state signal of the voltage controlled oscillator.

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Inventors:

KOBAYASHI YUKIO

Application Number:

JP23262591A

Publication Date:

October 06, 1999

Filing Date:

September 12, 1991

Export Citation:

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Assignee:

NIPPON DENKI KK

International Classes:

H03L7/095; H03L7/089; H03L7/091; H03L7/107; (IPC1-7): H03L7/089; H03L7/095; H03L7/107

Domestic Patent References:

JP391320A
JP1215121A
JP52156436U

Attorney, Agent or Firm:

Naoki Kyomoto (2 outside)

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