To provide a phase synchronization circuit capable of preventing an output of a count whose phase is deviated at start and recovering a deviated phase relation due to an external disturbance or the like.

Counters 10, 20 receive a clock signal, and each counter counts the number of clock signal pulses and outputs counts CNT1, CNT2. A comparator 30 compares the counts CNT1, CNT2 and provides an output of a signal SCMP, which is fed to a counter 10 via a gate circuit 40. When the counts CNT1, CNT2 are dissident, stepping of the count CNT1 is stopped on the basis of a signal CMP outputted from the comparator 30. Only the count CNT2 is circulated in this state and when the count CNT2 is coincident with the count CNT1, the stepping of the count CNT1 is started. Thus, the count CNT1 reaches a phase synchronization state with the count CNT2 and continues stepping.